View MAX2369_291043.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-1924; Rev 1; 10/01
Complete Dual-Band Quadrature Transmitter
General Description
The MAX2369 is a dual-band, triple-mode complete transmitter for cellular phones. The device takes a differential I/Q baseband input and mixes it up to IF through a quadrature modulator and IF variable-gain amplifier (VGA). The signal is then routed to an external bandpass filter and upconverted to RF through an SSB mixer and RF VGA. The signal is further amplified with an on-board PA driver. The MAX2369 is designed for dual-band operation and supports TDMA for the PCS band as well as TDMA and AMPS for the cellular band. The desired mode of operation is selected by loading data on the SPITM/ MICROWIRETM-compatible 3-wire serial bus. The MAX2369 then routes the signals to the appropriate ports depending on which band is selected. The MAX2369 includes two RF LO input ports and two PA driver ports, eliminating the need for external switching circuitry. The MAX2369 takes advantage of the serial bus to set modes such as charge-pump current, high or low sideband injection, and IF/RF gain balancing. It is packaged in a small (7mm 7mm) 48-pin QFN package with exposed paddle. o Dual-Band, Triple-Mode Operation o +7dBm Output Power with -34dBc ACPR (NADC Modulation) o 100dB Power Control Range o Supply Current Drops as Output Power Is Reduced o On-Chip IF VCO and IF PLL o QSPI/SPI/MICROWIRE-Compatible 3-Wire Bus o Digitally Controlled Operational Modes o +2.7V to +5.5V Operation o Single Sideband Upconverter Eliminates SAW Filters o Power Control Distributed at IF and RF for Optimum Dynamic Range
Features
MAX2369
Ordering Information
PART MAX2369EGM TEMP. RANGE -40C to +85C PIN-PACKAGE 48 QFN-EP*
Applications
Dual-Band TDMA/Amps Handsets GAIT Handsets
*Exposed paddle
Functional Diagram
N.C. VCC GND VCC
42 41 40 39
GND GND GND
48
47
46
45
44
43
38
Wireless Data Links (WAN/LAN) Wireless Local Area Networks (LANs) High-Speed Data Modems High-Speed Digital Cordless Phones Wireless Local Loop (WLL)
RFL RFH LOCK VCC VCC VCC TXGATE IFIN+ IFINN.C. N.C. RBIAS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
0

37
Satellite Phones
GND LOL LOH
IFCP VCC
Triple-Mode, Dual-Mode, or Single-Mode Mobile Phones
36
IFPLL
35 34 33 32 31
MAX2369
90 0 +45 -45 /2
30 29 28
90 /2
Pin Configuration appears at end of data sheet. Selector Guide appears at end of data sheet.
27 26 25
REF N.C. N.C. N.C. N.C. TANK+ TANKIFLO VCC SHDN II+
IFOUT+ IFOUT-
CLK DI
CS VCC VCC
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
VGC VCC VCC
Q+ Q-
1
For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Complete Dual-Band Quadrature Transmitter MAX2369
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +3.6V RFL, RFH.............................................................................+5.5V DI, CLK, CS, VGC, SHDN, TXGATE, LOCK.....................................................-0.3V to (VCC + 0.3V) AC Input Pins (IFIN, Q, I, TANK, REF, LOL, LOH) ...............................................................1.0V peak Digital Input Current (SHDN, TXGATE, CLK, DI, CS) ................................................................10mA Continuous Power Dissipation (TA = +70C) 48-Pin QFN-EP (derate 27mW/C above +70C) ..............2.5W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(MAX2369 Test Fixture: VCC = VBATT = +2.75V, SHDN = TXGATE = +2.0V, VGC = +2.5V, RBIAS = 16k, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C, and operating modes are defined in Table 6.)
PARAMETER Operating Supply Voltage VGC = 0.5V PCS mode VGC = 2.0V VGC = 2.5V VGC = 0.5V (Note 1) Operating Supply Current FM mode Cellular digital mode VGC = 2.0V VGC = 2.5V VGC = 0.5V VGC = 2.0V VGC = 2.5V Addition for IFLO buffer TXGATE = 0.6V SHDN = 0.6V, sleep mode Logic High Logic Low Logic Input Current VGC Input Current VGC Input Resistance During Shutdown Lock Indicator High Lock Indicator Low SHDN = 0.6V 50k pullup load 50k pullup load -5 -12 200 VCC - 0.4 0.4 280 2.0 0.6 +5 +12 CONDITIONS MIN 2.7 80 85 120 82 87 123 77 80 105 6.5 16 0.5 TYP MAX 3.0 106 112 150 107 113 155 101 105 133 11 25 20 A V V A A k V V mA UNITS V
2
_______________________________________________________________________________________
Complete Dual-Band Quadrature Transmitter
AC ELECTRICAL CHARACTERISTICS
(MAX2369 Evaluation Kit: 50 system, operating modes as defined in Table 6, input voltage at I and Q = 200mVRMS differential, common mode = VCC/2, 300kHz quadrature CW tones, IF synthesizer locked with passive lead-lag second-order loop filter, REF = 200mVp-p at 19.44MHz, VCC = SHDN = CS = TXGATE = +2.75V, VBAT = +2.75V, IF output load = 400, LOH, LOL input power = -7dBm, fLOL = 1017.26MHz, fLOH = 2061.26MHz, IFIN = 125mVRMS at 181.26MHz, IS-136 TDMA modulation, fRFH = 1880MHz, fRFL = 836MHz, TA = +25C, unless otherwise noted.)
PARAMETER IF Frequency Range I/Q Common-Mode Input Voltage IF Gain Control Range IF Output Power, Digital Mode Gain Variation Over Temperature RX Band Noise Power Carrier Suppression Sideband Suppression MODULATOR, FM MODE IF Gain Control Range Output Power UPCONVERTER AND PREDRIVER IF Frequency Range Low-Band Frequency Range High-Band Frequency Range LOL Frequency Range LOH Frequency Range Output Power, RFL (Note 4) VGC = 2.5V, NADC modulation, ACPR < -32dBc/ -55dBc at +30kHz/+60kHz offset VGC = 2.5V, FM mode VGC = 2.6V, NADC modulation, ACPR = -32dB/ -55dBc at +30kHz/+60kHz offset VGC = 0.5V to 2.5V Relative to +25C, TA = -40C to +85C (Note 4) RFL RFH RFL, VGC = 2.5V RFH, VGC = 2.6V RFL, VGC = 2.5V RFH, VGC = 2.6V -133 -134 -25 -24 -22 -24 5.8 9 4 RFL port RFH port 120-235 800-1000 1700-2000 800-1150 1400-2300 7 12 6.6 30 3 dBm dB dB dBc dBm dBm/ Hz MHz MHz MHz MHz MHz dBm VGC = 0.5V to 2.5V, IFG = 100 VGC = 2.5V, IFG = 111, I/Q modulation VGC = 2.5V, IFG = 111, direct VCO modulation 85 -8.5 -5.5 dB dBm VCC = 2.7V to 3.0V (Notes 2, 3, 4) VGC = 0.5V to 2.5V, IFG = 100 VGC = 2.5V, IFG = 100 Relative to +25C, TA = -40C to +85C (Note 4) VGC = 2.5V, IFG = 100, FIF = 181.26MHz, noise measured at FIF 20MHz VGC = 2.5V, IFG = 100 VGC = 2.5V, IFG = 100 30 30 1.35 CONDITIONS MIN TYP 120-235 VCC / 2 85 -10 0.8 -145 49 38 VCC - 1.25 MAX UNITS MHz V dB dBm dB dBm/Hz dB dB
MAX2369
MODULATOR, QUADRATURE MODES (Digital Cellular, Digital PCS, FM IQ)
Output Power, RFH (Note 4) Power-Control Range Gain Variation Over Temperature RF Image Rejection (Note 4) LO Leakage (Note 4) RX Band Noise Power
_______________________________________________________________________________________
3
Complete Dual-Band Quadrature Transmitter MAX2369
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX2369 Evaluation Kit: 50 system, operating modes as defined in Table 6, input voltage at I and Q = 200mVRMS differential, common mode = VCC/2, 300kHz quadrature CW tones, IF synthesizer locked with passive lead-lag second-order loop filter, REF = 200mVp-p at 19.44MHz, VCC = SHDN = CS = TXGATE = +2.75V, VBAT = +2.75V, IF output load = 400, LOH, LOL input power = -7dBm, fLOL = 1017.26MHz, fLOH = 2061.26MHz, IFIN = 125mVRMS at 181.26MHz, IS-136 TDMA modulation, fRFH = 1880MHz, fRFL = 836MHz, TA = +25C, unless otherwise noted.)
PARAMETER IF_PLL Reference Frequency Frequency Reference Signal Level IF Main Divide Ratio IF Reference Signal Ratio VCO Operating Range IF LO Output Power Charge-Pump Source/Sink Current BUF_EN = 1 ICP = 00 ICP = 01 ICP = 10 ICP = 11 Turbolock Boost Current Charge-Pump Source/Sink Matching Charge-Pump High-Z Leakage (Note 5) Locked, all values of ICP, over specified compliance range (Note 6) Over specified compliance range (Note 6) 148 185 295 385 385 5 0.1 256 2 240-470 -6 200 260 400 530 530 5 10 260 345 515 700 700 A % nA A 30 0.6 16384 2048 MHz dBm MHz Vp-p CONDITIONS MIN TYP MAX UNITS
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6:
See Table 6 for register settings. ACPR is met over the specified VCM range. VCM must be supplied by the I/Q baseband source with 6A capability. Guaranteed by design and characterization. When enabled, turbolock is active during acquisition and injects boost current in addition to the normal charge-pump current. Charge Pump Compliance range is 0.5V to VCC - 0.5V.
4
_______________________________________________________________________________________
Complete Dual-Band Quadrature Transmitter
Typical Operating Characteristics
(MAX2369EVKIT, VCC = +2.8V, VBAT = 3.0V, TA = +25C, unless otherwise noted.)
IF PLL SETTLING TIME
MAX2369 toc01
MAX2369
TANK 1/S11 vs. FREQUENCY
MAX2369 toc02
ICC vs. VGC INPUT
MAX2369 toc03
10 8 FREQUENCY DEVIATION (kHz) 6 4 2 0 -2 -4 -6 -8 -10 fIF = 181.26MHz
140 130 120 ICC (mA) 110 100 90 PCS CELLULAR
5 4 3 2 1 z0 = 200
0 100 200 300 400 500 600 700 800 900 1000 TIME (s)
EQUIVALENT PARALLEL R-C 1: 200MHz, 1.76k, 0.26pF 2: 260MHz, 1.66k, 0.31pF
3: 330MHz, 1.58k, 0.34pF 4: 780MHz, 1.21k, 0.43pF 5: 1GHz, 0.94k, 0.47pF
80 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 VGC (V)
OUTPUT POWER vs. VGC INPUT
MAX2369 toc04
IF OUTPUT POWER vs. VGC INPUT AND IF DAC SETTING
MAX2369 toc05
IF OUTPUT POWER vs. VGC INPUT
-40C
MAX2369 toc06
10 5 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 1.5
0 -20 -40 POUT (dBm) -60 -80 -100 011 -120 111 101 001 010 110 100
0 -10 -20 -30 IF POWER (dBm) -40 -50 -60 -70 -80 -90 -100 -110 +25C 0 0.5 1.0 1.5
OUTPUT POWER (dBm)
CELLULAR
+85C
000
PCS
1.7
1.9
2.1 VGC (V)
2.3
2.5
0
0.5
1.0
1.5 VGC (V)
2.0
2.5
3.0
2.0
2.5
3.0
VGC (V)
IF OUTPUT POWER vs. VGC INPUT
MAX2369 toc07
SIDEBAND SUPPRESSION AND LO FEEDTHROUGH (IFOUT)
-10 -20 -30 POUT (dBm) -40 -50 -60 -70 -80 -90 SIDEBAND LO DESIRED
MAX2369 toc08
0 -20 2.7V, 3.0V, 3.3V -40 POUT (dBm) -60 -80 -100 -120 0 0.5 1.0 1.5 VGC (V) 2.0 2.5
0
3.0
-100 181.21
181.23
181.25
181.27
181.29
181.31
FREQUENCY (MHz)
_______________________________________________________________________________________
5
Complete Dual-Band Quadrature Transmitter MAX2369
Typical Operating Characteristics (continued)
(MAX2369EVKIT, VCC = +2.8V, VBAT = 3.0V, TA = +25C, unless otherwise noted.)
PHASE NOISE LOW-BAND OSCILLATOR vs. FREQUENCY OFFSET (181.26MHz)
MAX23669 toc09 MAX2369 toc10
I/Q BASEBAND FREQUENCY RESPONSE
0 -0.5 -1.0 (dBc) -1.5 -2.0 -2.5 -3.0 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY (MHz) -50 -60 -70 PHASE NOISE (dBc/Hz) -80 -90 -100 -110 -120 -130 -140 -150
RFL OUTPUT SPECTRUM
10 0 AMPLITUDE (dBm) -10 -20 -30 -40 -50 -60 -70 -80 LO IMAGE DESIRED
MAX2369 toc11
20
FCOMP = 360kHz
0.001
0.01
0.1
1
10
500
700
900
1100
1300
1500
OFFSET FREQUENCY (MHz)
FREQUENCY (MHz)
RFH OUTPUT SPECTRUM
MAX2369 toc12
CASCADED ACPR/ALT vs. POWER (RFL)
MAX2369 toc13
CASCADED ACPR/ALT vs. POWER (RFH)
ACPR WITH ROOT RAISED COSINE FILTER ACPR WITHOUT ROOT RAISED COSINE FILTER
MAX2369 toc14
10 0 -10 AMPLITUDE (dBm) -20 -30 -40 -50 -60 -70 -80 -90 1500 1700 1900 2100 2300 LO DESIRED IMAGE
-20 -30 -40 ACPR (dBc) -50 -60 -70 -80 ACPR WITH ROOT RAISED COSINE FILTER ACPR WITHOUT FILTER
-20 -30 ACPR/ALT (dBc) -40 -50 -60 -70
ALT WITH OR WITHOUT FILTER -80 -20 -16 -12 -8 -4 0 4 8
ALT WITH OR WITHOUT ROOT RAISED COSINE FILTER -24 -20 -16 -12 -8 -4 0 4 6
2500
FREQUENCY (MHz)
POWER (dBm)
POWER (dBm)
LOL PORT S11
MAX2369 toc17
LOH PORT S11
MAX2369 toc18
5 4 4 321 3 21
1: 2: 3: 4:
700MHz, 72 -j51 966MHz, 60 -j46 1.22MHz, 52 -j38 1.5GHz, 40 -j25
1600MHz TO 2500MHz 1: 1.6GHz, 40 -j25 2: 1.75GHz, 36 -j22 3: 1.88GHz, 34 -j18 4: 2.01GHz, 32 -j15 5: 2.5GHz, 29 -j0
6
_______________________________________________________________________________________
Complete Dual-Band Quadrature Transmitter
Pin Description
PIN 1 NAME RFL FUNCTION Transmitter RF Output for Cellular Band (800MHz to 1000MHz)--for both FM and digital modes. This open-collector output requires a pullup inductor to the supply voltage, which is part of the output matching network and may be connected directly to the battery. Transmitter RF Output for PCS Band (1700MHz to 2000MHz). This open collector output requires a pullup inductor to the supply voltage. The pullup inductor is part of the output matching network and may be connected directly to the battery. Open-Collector Output Indicating Lock Status of the IF PLL. Requires a pullup resistor. Control using configuration register bit LD_MODE. Power Supply. Supply pin for the driver stage. VCC must be bypassed to system ground as close to the pin as possible. The ground vias for the bypass capacitor should not be shared by any other branch. Bypass to ground with 100pF and 100nF capacitors. Power Supply. Connect to pin 4 for normal operation. Supply Pin for the Upconverter Stage. VCC must be bypassed to system ground as close to the pin as possible. The ground vias for the bypass capacitor should not be shared by any other branch. Digital Input. A logic low on TXGATE shuts down everything except the IF PLL, IF VCO, and serial bus and registers. This mode is used for IF PLL settling before the transmit time slot. Differential Inputs to the RF Upconverter. These pins are internally biased to +1.5V. The input impedance for these ports is nominally 400 differential. The IF filter should be AC-coupled to these ports. Keep the differential lines as short as possible to minimize stray pickup and shunt capacitance. No Connection. Leave these pins floating. Bias Resistor Pin. RBIAS is internally biased to a bandgap voltage of +1.18V. An external resistor or current source must be connected to this pin to set the bias current for the upconverters and PA driver stages. The nominal resistor value is 16k. This value can be altered to optimize the linearity of the driver stage. Input Pins from the 3-Wire Serial Bus (SPI/QSPI/MICROWIRE compatible). An R-C filter on each of these pins may be used to reduce noise. Power supply. Bypass to ground with a 1000pF capacitor. Differential IF Outputs. These pins must be inductively pulled up to VCC. A differential IF bandpass filter is connected between this port and IFIN+ and IFIN-. The pullup inductors can be part of the filter structure. The differential output impedance of this port is nominally 600. The transmission lines from these pins should be short to minimize the pickup of spurious signals and noise. RF and IF Variable-Gain Control Analog Input. VGC floats to +1.5V. Apply +0.5V to +2.6V to control the gain of the RF and IF stages. An RC filter on this pin may be used to reduce DAC noise or PDM clock spurs from this line. Supply Pin for the IF VGA. Bypass with a capacitor as close to the pin as possible. The bypass capacitor must not share its ground vias with any other branches.
MAX2369
2
RFH
3
LOCK
4 5 6
VCC VCC VCC TXGATE
7
8, 9
IFIN+, IFIN-
10, 11
N.C.
12
RBIAS
13, 14, 15 16, 17
CLK, DI, CS VCC
18, 19
IFOUT+, IFOUT-
20
VGC
21
VCC
_______________________________________________________________________________________
7
Complete Dual-Band Quadrature Transmitter MAX2369
Pin Description (continued)
PIN 22 23, 24 25, 26 27 28 29 30, 31 32, 33, 34, 35, 42 36 NAME VCC Q+, QI+, ISHDN VCC IFLO TANK-, TANK+ N.C. REF FUNCTION Supply for the I/Q Modulator. Bypass with capacitor as close to the pin as possible. The bypass capacitor must not share its ground vias with any other branches. Differential Q-Channel Baseband Inputs to the Modulator. These pins go directly to the bases of a differential pair and require an external common-mode bias voltage. Differential I-Channel Baseband Inputs to the Modulator. These pins go directly to the bases of a differential pair and require an external common-mode bias voltage. Shutdown Input. A logic low on SHDN shuts down the entire IC. An R-C lowpass filter may be used to reduce digital noise. Supply Pin to the VCO Section. Bypass as close to the pin as possible. The bypass capacitor should not share its vias with any other branches. Buffered LO Output. Control the output buffer using register bit BUF_EN and the divide ratio using the register bit BUF_DIV. Differential Tank Pins for the IF VCO. These pins are internally biased to +1.6V. No Connection. Leave these pins floating. Reference Frequency Input. REF is internally biased to VCC - 0.7V and must be AC-coupled to the reference source. This is a high-impedance port (25k II 3pF). Supply for the IF Charge Pump. This supply can differ from the system VCC. Bypass as close to the pin as possible. The bypass capacitor must not share its vias with any other branches. High-Impedance Output of the IF Charge Pump. Connect to the tune input of the IF VCOs through the IF PLL loop filter. Keep the line from IFCP to the tune input as short as possible to prevent spurious pickup, and connect the loop filter as close to the tune input as possible. Supply Pin for Digital Circuitry. Bypass as close to the pin as possible. The bypass capacitor must not share its vias with any other branch. Ground. Connect to PC board ground plane. Supply Pin. Bypass as close to the pin as possible. The bypass capacitor may share with supply pin for digital circuitry, pin 39. High-band RF LO Input Port. AC-couple to this port. Low-band RF LO Input Port. AC-couple to this port. DC and AC GND Return for the IC. Connect to PC board ground plane using multiple vias.
37
VCC
38
IFCP
39 40, 45, 46, 47, 48 41 43 44 Exposed paddle
VCC GND VCC LOH LOL GND
8
_______________________________________________________________________________________
Complete Dual-Band Quadrature Transmitter
Detailed Description
The MAX2369 complete quadrature transmitter accepts differential I/Q baseband inputs with external commonmode bias. A modulator upconverts this to IF frequency in the 120MHz to 235MHz range. A gain control voltage pin (VGC) controls the gain of both the IF and RF VGAs simultaneously to achieve best noise and linearity performance. The IF signal is brought off-chip for filtering, then fed to a single sideband upconverter followed by the RF VGA and PA driver. The RF upconverter requires an external VCO for operation. The IF PLL and operating mode can be programmed by an SPI/QSPI/ MICROWIRE-compatible 3-wire interface. The following sections describe each block in the MAX2369 Functional Diagram. Use high-Q inductors and varactors to maximize equivalent parallel resistance. The ICP_MAX bit in the OPCTRL register can be set to 1 to increase the charge pump current.
MAX2369
IF VGA
The IF VGA allows varying an IF output level that is controlled by the VGC voltage. The voltage range on VGC of +0.5V to +2.6V provides a gain-control range of 85dB. The IF output ports from the VGA are optimized for IF frequency from 120MHz to 235MHz. IFOUT ports support direct VCO FM modulation. The differential IF output port has an output impedance of 600 when pulled up to VCC through a choke.
Single Sideband Mixer
The RF transmit mixer uses a single sideband architecture to eliminate an off-chip RF filter. The mixer is followed by the RF VGA. The RF VGA is controlled by the same VGC pin as the IF VGA to provide optimum linearity and noise performance. The total power control range is >100dB.
I/Q Modulator
Differential in-phase (I) and quadrature-phase (Q) input pins are designed to be DC-coupled and biased with the baseband output from a digital-to-analog converter (DAC). I and Q inputs need a DC bias of VCC/2 and a current-drive capability of 6A. Common-mode voltage will work within a 1.35V to (VCC - 1.25V) range. Typically, I and Q will be driven differentially with a 200mVRMS baseband signal. Optionally, I and Q may be programmed for 100mVRMS operation with the IQ_LEVEL bit in the configuration register. The IF VCO output is fed into a divide-by-two/quadrature generator block to derive quadrature components to drive the IQ modulator. The output of the modulator is fed into the VGA.
PA Driver
The MAX2369 includes two power-amplifier (PA) drivers. Each is optimized for the desired operating frequency. RFL is optimized for cellular-band operation. RFH is optimized for PCS operation. The PA drivers have open-collector outputs and require pullup inductors. The pullup inductors can act as the shunt element in a shunt series match.
IF VCO
The VCO oscillates at twice the desired IF frequency. Oscillation frequency is determined by external tank components (see Applications Information). Typical phase-noise performance for the tank is shown in Typical Operating Characteristics.
Programmable Registers
The MAX2369 includes five programmable registers consisting of two divide registers, a configuration register, an operational control register, and a test register. Each register consists of 24 bits. The 4 least significant bits (LSBs) are the register's address. The 20 most significant bits (MSBs) are used for register data. All registers contain some "don't care" bits. These can be either a zero or a 1 and do not affect operation (Figure 1). Data is shifted in MSB first, followed by the 4-bit address. When CS is low, the clock is active and data is shifted with the rising edge of the clock. When CS transitions to high, the shift register is latched into the register selected by the contents of the address bits. Power-up defaults for the five registers are shown in Table 1. The registers should be initialized according to Table 2. The dividers and control registers are programmed from the SPI/QSPI/MICROWIRE-compatible serial port.
IFLO Output Buffer
IFLO provides a buffered LO output when BUF_EN is 1. The IFLO output frequency is equal to the VCO frequency when BUF_DIV is 0, and half the VCO frequency when BUF_DIV is 1. The output power is -6dBm. This output is used in test mode.
IF PLL
The IF PLL uses a charge-pump output to drive a loop filter. The loop filter will typically be a passive secondorder lead lag filter. Outside the filter's bandwidth, phase noise will be determined by the tank components. The two components that contribute most significantly to phase noise are the inductor and varactor.
_______________________________________________________________________________________
9
Complete Dual-Band Quadrature Transmitter MAX2369
The IFM register sets the main frequency divide ratio for the IF PLL. The IFR register sets the reference frequency divide ratio. The IF VCO frequency can be determined by the following: IF VCO frequency = fREF (IFM / IFR) where fREF is the external reference frequency. The operational control register (OPCTRL) controls the state of the MAX2369. See Table 3 for the function of each bit. The configuration register (CONFIG) sets the configuration for the IF PLL and the baseband I/Q input levels See Table 4 for a description of each bit. The test register is not needed for normal use. Power Management Bias control is distributed among several functional sections and can be controlled to accommodate many different power-down modes as shown in Table 5. The shutdown control bit is of particular interest since it differs from the SHDN pin. When the shutdown control bit is active (SHDN_BIT = 0), the serial interface is left active so that the part can be turned on with the serial bus while all other functions remain shut off. In contrast,
MSB B19 B18 B17 B16 B15 B14 B13 B12 B11 B10
24 BIT REGISTER DATA 20 BITS B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 A3 A2 A1
LSB ADDRESS 4 BITS A0
IFM DIVIDE RATIO REGISTER (14 BITS) X X X X X X B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0
ADDRESS 0 1 0
IFR DIVIDE RATIO REGISTER (11 BITS) X X X X X X X X X B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0
ADDRESS 0 1 1
CONTROL REGISTER (16 BITS) X X X X B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0
ADDRESS 1 0 0
CONFIGURATION REGISTER (16 BITS) X X X X B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0
ADDRESS 1 0 1
TEST REGISTER (8 BITS) X X X X X X X X X X X X B7 B6 B5 B4 B3 B2 B1 B0 0
ADDRESS 1 1 1
X = DON'T CARE
Figure 1. Register Configuration
Table 1. Register Power-Up Default States
REGISTER IFM IFR OPCTRL CONFIG TEST DEFAULT 6519 dec 0492 dec 892F hex D03F hex 0000 hex ADDRESS 0010b 0011b 0100b 0101b 0111b FUNCTION IF M divider count IF R divider count Operational control settings Configuration and setup control Test-mode control
Table 2. Register Initialization for FREF = 19.44MHz, FIF = 181.26MHz, FCOMP = 360kHz
REGISTER IFM IFR OPCTRL CONFIG TEST DEFAULT 1007 dec 0054 dec 890F hex 903D hex 0000 hex ADDRESS 0010b 0011b 0100b 0101b 0111b FUNCTION IF M divider count IF R divider count Operational control settings Configuration and setup control Test-mode control
10
______________________________________________________________________________________
Complete Dual-Band Quadrature Transmitter
when the SHDN pin is low it shuts down everything. In either case, PLL programming and register information is lost. To retain the register information, use standby mode (STBY = 0). Signal Flow Control Table 6 shows an example of key registers for triplemode operation.
Applications Information
The MAX2369 is designed for use in dual-band, triplemode systems. It is recommended for triple-mode handsets. A typical application circuit is shown in Figure 2.
MAX2369
3-Wire Interface
Figure 3 shows the 3-wire interface timing diagram. The 3-wire bus is SPI/QSPI/MICROWIRE compatible.
VCC
VCC PCS OUTPUT 48 1 CELLULAR OUTPUT VCC LOCK OUTPUT 2 3 RFL RFH GND 47 GND 46 GND 45 44 43 LOH 42 N.C.
FRAC-N PLL VCC VCC VCC
41 VCC
40 GND
39 VCC
38
37 REF 36
GND LOL
IFCP VCC
N.C. 35 IF PLL N.C. 34 90 0 N.C. 33 N.C. 32 TANK+ LOOP FILTER
LOCK
4 VCC VCC 5 6 TXGATE LOGIC INPUT 7 8 9 BIAS CTRL VCC VCC 45 TXGATE IFIN+ IFIN-
MAX2369
-45 TANK/2
31 TANK 30 29 IFLO VCC 28 SHDN 27 SHDN LOGIC INPUT VCC
10 N.C. 11 N.C. 12 RBIAS CLK 13 DI 14 CS 15 VCC 16 VCC 17 VCC DAC GAIN CONTROL INPUT IFOUT+ IFOUT- VGC VCC 18 19 20 21 VCC 22 VCC Q+ 23 0 90 /2
II+ Q24
26 25
Figure 2. MAX2369 Typical Application Circuit
______________________________________________________________________________________
11
Complete Dual-Band Quadrature Transmitter MAX2369
Table 3. Operation Control Register (OPCTRL)
BIT NAME LO_SEL UNUSED POWER-UP STATE 1 0 BIT LOCATION (0 = LSB) 15 14 FUNCTION 1 selects LOL input port; 0 selects LOH port. Set to 0 for normal operation. 1 keeps IF turbo-mode current active even when frequency acquisition is achieved. This mode is used when high operating IF charge-pump current is needed. Sets operating mode according to the following: 00 = FM mode 01 = Cellular digital mode; RFL is selected 10 = Not used 11 = PCS mode; RFH is selected Set to 0 for normal operation. Set to 0 for normal operation. 3-bit IF gain control. Alters IF gain by approximately 2dB per LSB (0 to 14dB). Provides a means for adjusting balance between RF and IF gain for optimized linearity. When this register is 1, the upper sideband is selected (LO below RF). When this register is 0, the lower sideband is selected (LO above RF). 0 turns IFLO buffer off; 1 turns IFLO buffer on. 0 selects direct VCO modulation. (IF VCO is externally modulated and the I/Q modulator is bypassed); 1 selects quadrature modulation. 0 shuts down everything except registers and serial interface. 0 shuts down modulator and upconverter, leaving PLL locked and registers active. This is the programmable equivalent to the TXGATE pin. 0 shuts down everything except serial interface, and also resets all registers to power-up state.
ICP_MAX
0
13
MODE
01
12, 11
UNUSED UNUSED IFG
0 0 100
10 9 8, 7, 6
SIDE_BAND BUF_EN MOD_TYPE STBY TXSTBY SHDN_BIT
1 0 1 1 1 1
5 4 3 2 1 0
12
______________________________________________________________________________________
Complete Dual-Band Quadrature Transmitter MAX2369
Table 4. Configuration Register (CONFIG)
BIT NAME IF_PLL_SHDN UNUSED UNUSED IQ_LEVEL BUF_DIV VCO_BYPASS POWER-UP STATE 1 1 0 1 0 0 BIT LOCATION (0 = LSB) 15 14 13 12 11 10 FUNCTION 0 shuts down the IF PLL. This mode is used with an external IF VCO and IF PLL. Set to 0 for normal operation. Set to 0 for normal operation. 1 selects 200mVRMS input mode; 0 selects 100mVRMS input mode. 1 selects /2 on IFLO port; 0 bypasses the divider. 1 bypasses IF VCO and enables a buffered input for external VCO use. A 2-bit register sets the IF charge-pump current as follows: 00 = 200A 01 = 260A 10 = 400A 11 = 530A Not used. Leave in the power-up/initialized state. IF phase-detector polarity; 1 selects positive polarity (increasing tuning voltage on the VCO produces increasing frequency); 0 selects negative polarity (increasing tuning voltage on the VCO produces decreasing frequency). Not used. Leave in the power-up/initialized state. Set to 0 for normal operation. Determines output mode for LOCK detector pin as follows: 0 = test mode, LD_MODE cannot be 0 for normal operation 1 = IF PLL lock detector
ICP
00
9, 8
UNUSED
00
7, 6
IF_PD_POL
1
5
UNUSED UNUSED LD_MODE
111 1 1
4, 3 ,2 1 0
Electromagnetic Compliance Considerations
Two major concepts should be employed to produce a noise-free and EMC-compliant transmitter: minimize circular current-loop area to reduce H-field radiation and minimize voltage drops to reduce E-field radiation. To minimize the circular current-loop area, bypass as close to the part as possible and use the distributed capacitance of a ground plane. To minimize voltage drops, make VCC traces short and wide, and make RF traces short. The "don't care" bits in the registers should be zero in order to minimize electromagnetic radiation due to unnecessary bit banging. RC filtering can also be used to slow the clock edges on the 3-wire interface, reducing high-frequency spectral content. RC filtering also provides for transient protection against IEC802 testing by shunting high frequencies to ground, while the
series resistance attenuates the transients for error-free operation. The same applies to the override pins (SHDN, TXGATE). When floating the override pins, bypass to ground with the capacitors as close to the part as possible. High-frequency bypass capacitors are required close to the pins with a dedicated via to ground. The 48-pin QFN-EP package provides minimal inductance ground by using an exposed paddle under the part. Provide at least five low-inductance vias under the paddle to ground to minimize ground inductance. Use a solid ground plane wherever possible. Any cutout in the ground plane may act as slot radiator and reduce its shield effectiveness. Keep the RF LO traces as short as possible to reduce LO radiation and susceptibility to interference.
______________________________________________________________________________________
13
Complete Dual-Band Quadrature Transmitter MAX2369
Table 5. Power-Down Modes
OFF UPCONVERTER IF LO BUFFER OPCTRL REG MODULATOR
POWER-DOWN MODES
COMMENTS
SHDN pin TXGATE pin IF PLL SHDN TX STBY REG STBY REG SHDN
Ultra-low shutdown current For punctured TX mode For external IF PLL use TX is off, but IF LO stays locked Shuts down, but preserves registers Serial bus is still active
X X X X X
X X
X
X
X
X
X X
X X
X X X X X X X X X X X X
Table 6. Register and Control Pin States for Key Operating Modes
OPCTRL REGISTER CONTROL PINS
IF_PLL_SHDN
MODE
DESCRIPTION MOD_TYPE SHDN_BIT TXSTBY LO_SEL
TXGATE H H H H L L X
MODE
PCS Digital Cellular Digital FM FM_IQ PCS TXGATE Cellular TXGATE Sleep
RFH selected RFL selected Direct VCO modulation, RFL selected FM with IQ modulation, RFL selected Gated transmission, PCS Gated transmission, cellular digital Everything off
0 1 1 1 0 1 X
11 01 00 00 11 01 XX
1 1 0 1 1 1 X
1 1 1 1 1 1 X
1 1 1 1 X X X
1 1 1 1 1 1 X
1 1 1 1 1 1 X
X = Don't care
14
______________________________________________________________________________________
SHDN H H H H H H L
STBY
CONFIG REG X
IF PLL REGS
SERIAL BUS
IF VCO
IF PLL
Complete Dual-Band Quadrature Transmitter MAX2369
DI B19 (MSB) B18 B0 A3 A1 A0 (LSB) tCS > 50ns tCH > 10ns tCWH > 50ns tES > 50ns tCWL > 50ns tEW > 50ns tEW
CLK tCWL tCS CS NOTE: THE 3-WIRE BUS IS SPI/QSPI/MICROWIRE-COMPATIBLE. tCH tCWH tES
Figure 3. 3-Wire Interface Diagram
CC
MAX2369
CD CCENT CD L CPAR CINT -Rn
Internal to the IC, the charge pump will have a leakage of less than 10nA. This is equivalent to a 300M shunt resistor. The charge-pump output must see an extremely high DC resistance of greater than 300M. This will minimize charge-pump spurs at the comparison frequency. Make sure there is no solder flux under the varactor or loop filter.
Layout Issues
CC
The MAX2369 EV kit can be used as a starting point for layout. For best performance, take into consideration power-supply issues, as well as the RF, LO, and IF layout.
Figure 4. Tank Port Oscillator
Power-Supply Layout IF Tank Design
To minimize coupling between different sections of the IC, the ideal power-supply layout is a star configuration, which has a large decoupling capacitor at a central VCC node. The VCC traces branch out from this node, each going to a separate VCC node in the MAX2369 circuit. At the end of each trace is a bypass capacitor with impedance to ground less than 1 at the frequency of interest. This arrangement provides local decoupling at each VCC pin. Use at least one via per bypass capacitor for a low-inductance ground connection.
The IF VCO tank (TANK+, TANK-) is fully differential. The external tank components are shown in Figure 4. The frequency of oscillation is determined by the following equation: 1 fOSC = 2 (CINT + CCENT + CVAR + CPAR ) L CVAR = CD x CC 2 (CD + CC )
Matching Network Layout
The layout of a matching network can be very sensitive to parasitic circuit elements. To minimize parasitic inductance, keep all traces short and place components as close to the IC as possible. To minimize parasitic capacitance, a cutout in the ground plane (and any other planes) below the matching network components can be used. On the high-impedance ports (e.g., IF inputs and outputs), keep traces short to minimize shunt capacitance.
CINT = Internal capacitance of TANK port CD = Capacitance of varactor CVAR = Equivalent variable tuning capacitance CPAR = Parasitic capacitance due to PC board pads and traces CCENT = External capacitor for centering oscillation frequency CC = External coupling capacitor to the varactor
______________________________________________________________________________________
15
Complete Dual-Band Quadrature Transmitter MAX2369
Tank Layout
Keep the traces coming out of the tank short to reduce series inductance and shunt capacitance. Keep the inductor pads and coupling capacitor pads small to minimize stray shunt capacitance.
TOP VIEW
N.C. VCC GND VCC IFCP VCC
42 41 40 39 38 37
Pin Configuration
GND GND GND
47 46
48
45
44
43
GND LOL LOH
RFL RFH LOCK VCC VCC VCC TXGATE IFIN+ IFINN.C. N.C. RBIAS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
36 35 34 33 32 31 30 29 28 27 26 25
REF N.C. N.C. N.C. N.C. TANK + TANK IFLO VCC SHDN II+
MAX2369
IFOUT+ IFOUT-
QFN-EP
Package Information
For the latest package outline information, go to www.maxim-ic.com/packages.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
VGC VCC VCC Q+ Q-
CLK DI
CS VCC VCC

▲Up To Search▲

Price & Availability of MAX2369

	To Download MAX2369 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .